• Workshop D43D

  • The D43D'2017, the 9th Workshop on Design for 3D Silicon Integration, will happen in Minatec on 26-27 June 2017. This year the D43D workshop will be attached to the Leti Days, and in strong association with the 50th anniversary of CEA-LETI.

    For more details to the 2017 Leti Days and the 50th anniversary of CEA-LETI, please check LetiDays.

    For the first time this year, the D43D workshop will share the technical program with the Leti Memory Workshop (LMW), with two common sessions on 3D Memory devices. For more details to the 2017 Memory Workshop, please check LMW.
  • Workshop Content
    3D IC is emerging as a promising approach to extend Moore’s law, overcome pin bandwidth limitations, and improve digital platform density and cost beyond a single chip. 3D IC as a technology, however, also introduces a number of key design, methodological, implementation and technological challenges that must be overcome to make them practical and cost-effective. As of today, 3D technology is getting more and more mature with 3D memory cubes, imagers, large size passive interposers. Nevertheless, new 3D technologies are appearing, with 3D memory devices, 3D High Density technologies, and Monolithic 3D technologies, opening a wild scope of new application spectrum, but also its new technical challenges.

    The D43D workshop is a two-day forum that brings together experts from both industry and academia to shed light on these near-term to long-term challenges and solutions and covers topics including, but not limited to : 3D technology, including the recent upcoming Monolithic 3D technology (CoolCubeTM), co-integration of 3D technology and recent 3D memory NVM devices, 3D architecture for Computing, interconnect architectures, thermal management, 3D for photonic, 3D for imager applications, design methodologies and tools, reliability and testing. The objective is to bring experts from both the industry and the academia to share recent results on the latest and most advanced 3D technologies.
  • Workshop Technical Program
    Program overview is given below.
    Schedule Monday 26 June Tuesday 27 June
    9:00 - 10:30   3D Technology Landscape and Advanced Imagers
    10:30 - 11:00   Coffee break
    11:00 - 12:30   3D for High Performance Computing
    12:30 - 14:00 Lunch Lunch
    14:00 - 15:30 3D Memory Devices Monolithic 3D : from Technology to Advanced Design
    15:30 - 16:00 Coffee break Coffee break
    16:00 - 17:30 3D Emerging Memories and New Architecture Paradigms 3D Design and Architecture

    * LMW workshop participants can also register and participate to D43D workshop 3D Memory Sessions (Monday 26 afternoon)
    Monday 26 June - Day 1
    12:30 - 14:00 Welcome Lunch
    13:45 - 14:00 Opening Session Pascal Vivet, CEA-LETI, France
    Session 1 3D Memory Devices
      Chair: Jean-Francois Roy, UPMEM, France  
    14:00 - 14:30 Non Volatile Memory: a wide spectrum of potential solutions Luca Perniola, CEA-LETI, France
    14:30 - 15:00 3D Memory : Patent Landscape Analysis Audrey Bastard, KNOWMADE, France
    15:00 - 15:30 Power, Heat, Reliability: A 3D Physical Design Perspective Aida Todri, LIRMM, France
    15:30 - 16:00 COFFEE BREAK
    Session 2 3D Emerging Memories and New Architecture Paradigms
      Chair : Bastien Giraud, CEA-LETI, France  
    16:00 - 16:30 Abundant-Data Computing: The N3XT 1,000X Subhasish Mitra, Stanford University, France
    16:30 - 17:00 Novel 3D technologies for the transition to cognitive systems Bert Offrein, IBM Zurich, Switzerland
    17:00 - 17:30 3D Memories: Now and Then! Christian Weiss,  University of Kaiserslautern, Germany
    Tuesday 27 June - Day 2
    8:45 - 9:00 Registration and Opening Pascal Vivet, CEA-LETI, France
    Session 3 3D Technology Landscape and Advanced Imagers
      Chair : Didier Lattard, CEA-LETI, France  
    9:00 - 9:30 Evolution and adoption of 3D TSV and 2.5D technology : From high performance to consumers applications Emilie Jolivet, YOLE, France
    9:30 - 10:00 Advanced 3D technologies for innovative 3D architecture S. Cheramy, CEA-LETI, France
    10:00 - 10:30 Smart imager: Computer vision integration with 3D stack  Jerome Chossat, STMicroelectronics, France
    10:30 - 11:00 COFFEE BREAK
    Session 4 3D for High Performance Computing
      Chair : Patrick Blouet, STMicroelectronics, France  
    11:00 - 11:30 Emerging architectures for computing with 3D silicon integration  Denis Dutoit, CEA-LETI, France
    11:30 - 12:00 2.5D/3D Systems with Silicon Photonic NoCs: Efficient Thermal Management, Opportunities, and Challenges Ayse Coskun, University of Boston, USA
    12:00 - 12:30 In-memory Computing with Majority RRAM Operations  Pierre-Emmanuel Gaillardon, University of Utah, USA
    12:30 - 14:00 LUNCH BREAK
    Session 5 Monolithic 3D : from Technology to Advanced Design
      Chair: Sébastien Thuriès, CEA-LETI, France  
    14:00 - 14:30 Technological status of monolithic 3D Perrine Batude, CEA-LETI, France
    14:30 - 15:00 Power, performance and area benefits of monolithic 3D-IC for equivalent Moore's Law scaling Shidhartha Das, ARM, UK
    15:00 - 15:30 On Efficient Ways to Use Commercial 2D IC EDA Tools to Build Commercial Quality Monolithic 3D IC Designs Sung Kyu Lim, Georgia Institute of Technology, USA
    15:30 - 16:00 COFFEE BREAK
    Session 6 3D Design and Tools
      Chair : Sung Kyu Lim, Georgia Institute of Technology, USA  
    16:00 - 16:25 Design Considerations and Noise Issues for Heterogeneous Contactless 3-D ICs Vasilis Pavlidis, Manchester University, UK
    16:25 - 16:50 Chip-to-chip communication on interposer based systems Andy Heinig, Fraunhofer Institute, Germany
    16:50 - 17:10 Modeling Challenges in Electrical Design of 3DIC based Systems Dusan Petranovic, Mentor Graphics, USA
    17:10 - 17:30 HANOI Whiteboard Flow: the Seed for 2.5D-IC Implementation Anna Fontanelli, Monozukiri, Italy
  • Workshop Committee
    General Chair:
    Pascal Vivet, CEA-LETI

    Program Chairs:
    Sébastien Thuriès, CEA-LETI
    Bastien Giraud, CEA-LETI

    Steering Committee:
    Ahmed Jerraya, CEA-LETI
  • Prior D43D workshops
  • About Leti
    Leti, a technology research institute at CEA Tech, is a global leader in miniaturization technologies enabling smart, energy-efficient and secure solutions for industry. Founded in 1967, Leti pioneers micro- and nanotechnologies, tailoring differentiating applicable solutions for global companies, SMEs and startups.
    Leti tackles critical challenges such as healthcare, energy and ICTs. From sensors to data processing and computing solutions, Leti’s multidisciplinary teams deliver solid expertise, leveraging world-class pre-industrialization facilities.
    With a staff of more than 1,900, a portfolio of 2,700 patents, 91,500 sq. ft. of cleanroom space and a clear IP policy, the institute is based in Grenoble, France, and has offices in Silicon Valley and Tokyo. Leti has launched 60 startups and is a member of the Carnot Institutes network.
    Contact us
    CEA / Leti
    17 rue des Martyrs
    38054 Grenoble cedex 9